Extending circuit for memory and transmitting-receiving device using extending circuit for memory

ABSTRACT

An Extending circuit for memory comprises: an output data effective signal generator  2  for, when a status signal STNF from a next-stage FIFO circuit represents a data writable state, asserting a write enable signal NWEO from the next-stage FIFO circuit, and enabling data to be written into the next-stage FIFO circuit; and an internal FIFO write enable generator  3  for receiving a status signal STNF from the next-stage FIFO circuit, when the next-stage FIFO circuit is in a data unwritable state, asserting an internal FIFO write enable signal S 3 , and enabling data to be written into the internal FIFO circuit  1.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an extending circuit for memoryand a transmitting-receiving device using the extending circuit formemory that are applied in digital data communication or the like.

[0003] 2. Description of the Related Art

[0004] In digital data communication, data processing speeds on atransmission side and a reception side should be equal with each otherin principle. In fields of particularly mobile communication and thelike, however, average data processing speeds on both sides are equalwith each other, but the processing speeds on both sides are differentfor short time. In such a case, FIFO (First In First Out) circuits areused in order to absorb the difference in the processing speeds. TheFIFO circuits are first in first out circuits for literally outputtingdata according to an input order. As a memory capacity of the FIFOcircuit is larger, a larger speed difference can be absorbedinstantaneously. Enlargement of the memory capacity, however, causesrise in the cost. Normally, a balance between the rise in the cost andthe processing ability is considered according to applications or thelike of the FIFO circuits, and the memory capacity is determined in afixed manner. In the case where the application of the FIFO circuits ischanged, some techniques for extending the memory capacity later aredisclosed (for example, see Japanese Patent Application Laid-Open No.05-020864 (1993) as Patent Document 1 which relates to the invention ofthis application).

[0005] In the above-mentioned prior technique, in the case or the likewhere the memory capacity of the FIFO circuit is insufficient, it isdifficult to extend the memory capacity later. As mentioned in thePatent Document 1, some techniques for extending the memory capacitylater are disclosed, but various restrictions are placed on theextension of the memory capacity. It is thus difficult to enlarge thememory capacity of the existent FIFO circuits instantly and simply.

SUMMARY OF THE INVENTION

[0006] It is, therefore, an object of the present invention to obtain anExtending circuit for memory which is capable of enlarging the memorycapacity instantly and simply as the need arises.

[0007] Further, there is a possibility that the memory capacity ofeither existent transmission FIFO circuit or reception FIFO circuit isinsufficient and the other one is sufficient depending on a change inservice condition of communication devices or the like. This state ispossibly reversed suddenly. In such a case, it is also the object of thepresent invention to realize a transmitting-receiving device usingextending circuit for memory which is capable of executing normaltransmission and reception using small memory capacity by instantlyconnecting the Extending circuit for memory with the reception FIFOcircuit or the transmission FIFO circuit in a switching manner.

[0008] According to the first aspect of the invention, to accomplish theabove object, there is provided an extending circuit for memory whichhas an internal FIFO circuit and is connected with an external FIFOcircuit, in order to extend memory capacity used for writing input data,comprising:

[0009] an output data effective signal generator which, when, based on astatus signal output from the external FIFO circuit, judged that theexternal FIFO circuit can write data, makes the external FIFO circuitperform writing operation, for outputting the input data into theexternal FIFO circuit; and

[0010] an internal FIFO write enable generator which, when, based on thestatus signal output from the external FIFO circuit, judged that theexternal FIFO circuit can not write data, makes the internal FIFOcircuit perform writing operation, for writing the input data into theinternal FIFO circuit.

[0011] Further, the extending circuit for memory may comprises:

[0012] an internal FIFO read enable generator which, when, based on thestatus signal output from the external FIFO circuit and a status signaloutput from the internal FIFO circuit, judged that the external FIFOcircuit can write data and the internal FIFO circuit is having memorydata, makes the internal FIFO circuit perform reading operation, forread the memory data out from the internal FIFO circuit and outputtingthe memory data to the external FIFO circuit; and

[0013] an output data generator which, when the external FIFO circuit isjudged being able to write data; and the internal FIFO circuit is judgedhaving memory data; and the input data is received, outputs, prior tothe input data, the memory data read out from the internal FIFO circuitto the external FIFO circuit.

[0014] According to the second aspect of the invention, to accomplishthe above object, there is provided a transmitting-receiving deviceusing extending circuit for memory for enabling the Extending circuitfor memory according to the above Extending circuit for memory to beconnected with either a transmission FIFO circuit or a reception FIFOcircuit in a switching manner in order to extend a memory capacity, thetransmitting-receiving device using extending circuit for memory usingthe Extending circuit for memory comprising:

[0015] a first selector for enabling either a transmission signal systemor a reception signal system to be connected with the Extending circuitfor memory in a switching manner;

[0016] a second selector for enabling a status signal from either thetransmission FIFO circuit or the reception FIFO circuit to be connectedwith the internal FIFO write enable generator, the output data effectivesignal generator, and the internal FIFO read enable generator of theExtending circuit for memory in a switching manner;

[0017] a third selector for enabling the transmission FIFO circuit to beconnected with either the output data generator and the output dataeffective signal generator of the Extending circuit for memory or thetransmission signal system in a switching manner; and

[0018] a fourth selector for enabling the reception FIFO circuit to beconnected with either the output data generator and the output dataeffective signal generator of the Extending circuit for memory or thereception signal system in a switching manner.

[0019] Further, the transmitting-receiving device using extendingcircuit for memory using the Extending circuit for memory may comprises:

[0020] a control section for:

[0021] receiving status signals from the transmission FIFO circuit andthe reception FIFO circuit, when the transmission FIFO circuit is in adata writable state and the reception FIFO circuit is in a dataunwritable state, connecting the first selector with the receptionsignal system and connecting the second and the third selectors with thereception selector in a switching manner, and

[0022] receiving the status signals from the transmission FIFO circuitand the reception FIFO circuit, when the reception FIFO circuit is in adata writable state and the transmission FIFO circuit is in a dataunwritable state, connecting the first selector with the transmissionsignal system and connecting the second and the third selectors with thetransmission selector in a switching manner.

[0023] The above and other objects and features of the present inventionwill become apparent from the following detailed description and theappended claims with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a block diagram of a constitution according to aconcrete example 1.

[0025]FIG. 2 is a time chart of an internal FIFO circuit.

[0026]FIG. 3 is a time chart of an Extending circuit for memory.

[0027]FIG. 4 is a connecting diagram of an FIFO module using theExtending circuit for memory.

[0028]FIG. 5 is a block diagram of a transmitting-receiving device usingextending circuit for memory using the Extending circuit for memory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Embodiments of the present invention are explained below bygiving concrete examples.

CONCRETE EXAMPLE 1

[0030] In this concrete example, in order to extending memory capacitywith respect to an existent FIFO circuit, an extending circuit formemory is provided, capable of realizing the extension of memory byconnecting instantly and simply to the existent FIFO circuit.Accordingly, with respect to the extending circuit for memory, theexistent FIFO circuit is used as an external FIFO circuit i.e. anext-stage FIFO circuit.

[0031] The following four functions are added to the Extending circuitfor memory in order to maintain a first in first out principle. (1) Whena next-stage FIFO circuit is in a writable state, namely, the next-stageFIFO circuit is empty, input data are transmitted directly to thenext-stage FIFO circuit. (2) When the next-stage FIFO circuit is in anunwritable state, namely, the next-stage FIFO circuit is full (notempty), input data are stored into an internal FIFO circuit.

[0032] (3) When the next-stage FIFO circuit is in a writable state,namely, the next-stage FIFO circuit is empty and data are stored in theinternal FIFO circuit, the data are transmitted to the next-stage FIFOcircuit. (4) When the next-stage FIFO circuit is in a writable state,namely, the next-stage FIFO circuit is empty, data are stored in theinternal FIFO circuit and the circuit receives the input data, the datastored in the internal FIFO circuit, serving as memory data aretransmitted to the next-stage FIFO circuit preferentially.

[0033] Further, the internal FIFO circuit and the added circuits foradding the above four functions are blocked so that they can beconnected with before and after the existent FIFO circuit instantly andsimply. An Input/Output node of the block is made to be similar to theexistent FIFO circuit. In order to achieve the above object, theExtending circuit for memory of the concrete example is constituted asfollows.

[0034]FIG. 1 is a block diagram of the constitution according to theconcrete example 1.

[0035] According to FIG. 1, the Extending circuit for memory 10 of theconcrete example 1 comprises an internal FIFO circuit 1, an output dataeffective signal generator 2, an internal FIFO write enable generator 3,an internal FIFO read enable generator 4, and an output data generator5.

[0036] The internal FIFO circuit 1 is similar to a prior (existent) FIFOcircuit, and has a CLK node for receiving a clock signal, a WE node forreceiving a write enable signal, a RE node for receiving a read enablesignal, a DIN node for receiving input data, a DOUT node for outputtingdata, and a ST node for outputting a difference between an internalwrite counter value and a read counter value as status signals.

[0037] Timing of signals at the respective nodes is explained withreference to the drawings.

[0038]FIG. 2 is a time chart of the internal FIFO circuit.

[0039]FIG. 2 shows signal states at the CLK node, the WE node, the REnode, the DIN node, the DOUT node, the ST node, the write counter andthe read counter in this order from top. The bottom part shows commontime areas in the respective signal states. One example of therespective signal states in the respective time areas is explained. Lowlevel (L level) at the WE node and the RE node are in an assertionstate.

[0040] Time Area “a”

[0041] Since both the WE node and the RE node are at a high level (Hlevel) and both the write counter and the read counter indicate zero,the ST node is maintained at 0.

[0042] Time Area “b”

[0043] The WE node is asserted (L level), and data 0 are input into theDIN node. The data 0 are stored in an internal memory (not shown).

[0044] Time Area “c”

[0045] The write counter counts the data 0 in the time area “b” withbeing delayed by one clock so as to indicate 1. The ST node, therefore,becomes 1.

[0046] Time Area “d”

[0047] While the WE node is at H level, the RE node is asserted (Llevel), and the data 0 stored in the internal memory are output from theDOUT node.

[0048] Time Area “e”

[0049] While the RE node is at H level, the WE node is asserted, anddata 1 are output into the DIN node. The data 1 are stored in theinternal memory. The read counter counts the data 0 in the time area “d”with being delayed by one clock so as to indicate 1. The ST terminal,therefore, becomes 0.

[0050] Time Area “f”

[0051] The WE node is asserted and data 2 are input into the DIN node.The data 2 are stored in the internal memory. Further, the RE node isasserted, and the data 1 stored in the time area “e” are output from theDOUT node. The write counter counts the data 1 in the time area “e” withbeing delayed by one clock so as to indicate 2. The ST counter,therefore, becomes 1.

[0052] Time Area “g”

[0053] While the WE node is at H level, the RE node is asserted, and thedata 2 stored in the time area “f” are output from the DOUT node. Thewrite counter counts the data 2 in the time area “f” with being delayedby one clock so as to indicate 3. The read counter counts the data 1 inthe time area “f” with being delayed by one clock so as to indicate 2.The ST counter, therefore, becomes 1.

[0054] The similar operation is repeated until the time area “h”.

[0055] As explained above, when the WE node is at L level (asserted),the input data (DIN) into the internal FIFO circuit 1 synchronize with aclock signal (CLK) so as to be stored in the internal memory. When theinput data are stored, the write counter increases by one with beingdelayed by one clock. Moreover, when the RE node is at L level(asserted), the data stored in the internal memory are read insynchronization with the clock signal (CLK). Further, the status signal(ST) represents a difference between a counted value of the writecounter and a counted value of the read counter, namely, a quantity ofthe data stored in the internal memory.

[0056] Again with reference to FIG. 1, the explanation as to theconstitution of the concrete example 1 is continued.

[0057] The output data effective signal generator 2 receives (monitors)a status signal (STNS) of a next-stage FIFO circuit, and asserts anext-stage FIFO write enable signal (WEn) when data can be written intothe next-stage FIFO circuit so as to enable the data to be written intothe next-stage FIFO circuit. That is to say, the output data effectivesignal generator 2 outputs an output data effective signal NWEOrepresenting whether data (DOUT) to be output to the Extending circuitfor memory 10 is effective or ineffective. The output data effectivesignal NWEO functions as a write enable signal (WEn) at the next stage.

[0058] A write enable signal (WEp) transmitted from a previous stage tothe Extending circuit for memory 10, a status signal S1 from theinternal FIFO circuit, a status signal STNF from a next-stage FIFOcircuit, and an internal FIFO read enable signal S2 output by theinternal FIFO read enable generator 4, mentioned later, are input intothe output data effective signal generator 2. When the internal FIFOread enable signal S2 is asserted (L level) or the next-stage FIFOcircuit is in a data writable state, namely, when the status signal ofthe next-stage FIFO is at H level, the output data effective signal NWEObecomes L level. This state is equivalent to that the write enablesignal (WEn) from the next-stage FIFO circuit is asserted.

[0059] The internal FIFO write enable generator 3 receives (monitors)the status signal (STNS) from the next-stage FIFO circuit, and assertsan internal FIFO write enable signal (S3) when the next-stage FIFOcircuit is in a data unwritable state, so as to enable input data (DIN)to be written into the internal FIFO circuit 1. A status signal (STNS)from the next-stage FIFO circuit and an internal FIFO read enable signalS2 output by the internal FIFO read enable generator 4, mentioned later,are input into the internal FIFO write enable generator 3.

[0060] When the next-stage status signal (STNF) is at L level (anext-stage memory is full), the internal FIFO write enable generator 3receives the write enable signal WEp from the previous stage, andasserts (L level) the internal FIFO write enable signal (S3). Moreover,also when the internal FIFO read enable signal S2 output by the internalFIFO read enable generator 4 is asserted, the internal FIFO write enablegenerator 3 receives the write enable signal WEp from the previous stageand asserts (L level) the internal write enable signal (S3).

[0061] The internal FIFO read enable generator 4 receives (monitors) astatus signal (STNF) from the next-stage FIFO circuit. When thenext-stage FIFO circuit is in a data writable state, the internal FIFOread enable generator 4 receives (monitors) the status signal (S1) fromthe internal FIFO circuit 1, and the internal memory is not empty, theinternal FIFO read enable generator 4 asserts the internal FIFO readenable signal (S2) so as to output the data stored in the memory.

[0062] The output data generator 5 receives input data and outputs theinput data to the next-stage FIFO circuit, and preferentially reads thedata stored in the internal FIFO circuit 1 instead of the input data soas to output them to the next-stage FIFO circuit when the internal FIFOread enable signal is asserted. This output becomes input data (DINn)into a next-stage FIFO circuit.

[0063] All the above components are integrated or made into a module, soas to compose the Extending circuit for memory 10. The node DIN receivesinput data, the node WCLK receives a clock signal, the node WEp receivesa previous-stage write enable signal, a node ST outputs a status signal,a node STNF receives a status signal from a next-stage FIFO circuit, anode NWEO outputs a write enable signal to the next-stage FIFO circuit,and the node DOUT outputs next-stage FIFO data.

Operation of Concrete Example 1

[0064]FIG. 3 is a time chart of the Extending circuit for memory.

[0065]FIG. 3 shows states of a clock signal (CLK), a write enable inputsignal (WEp), an internal FIFO read enable signal (S2), an internal FIFOwrite enable signal (S3), a next-stage FIFO status signal (STNF), anoutput data effective signal (NWEO), an input data (DIN), an internalFIFO output data (S4), an output data (DOUT), and an internal FIFOstatus signal (S1) in this order from the top. The bottom portion showstime areas common in the respective signals. L levels of the signalsWEp, S2 and S3 are in an assertion state. When the STNF signal is at Llevel, the next-stage FIFO circuit is full (in an unwritable state). Oneexample of the signal states in the time areas is explained.

[0066] Time Area A

[0067] The write enable signal (WEp) is asserted, and 0 is received asinput data (DIN). Since a next-stage FIFO status signal (STNF) is at Hlevel, the next-stage FIFO circuit is in a data writable state. Theinput data (DINO), therefore, are not stored in the internal FIFOcircuit and pass directly through the output data generator 5 so as tobe output (DOUT) as input data (DINn). Moreover, since the next-stageFIFO circuit is in a data writable state (STNF is at H level), theoutput data effective signal generator 2 sets the output data effectivesignal (NWEO) at L level. This state is such that the write enablesignal (WEn) from the next-stage FIFO circuit is asserted.

[0068] Time Area B

[0069] The write enable signal (WEp) is asserted, but since thenext-stage FIFO status signal (STNF) is at L level, the next-stage FIFOcircuit is in a data unwritable state. The output data effective signalgenerator 2, therefore, sets the output data effective signal (NWEO) atH level. This state is such that the write enable signal (WEn) from thenext-stage FIFO circuit is not asserted. Alternatively, the internalFIFO write enable generator 3 asserts the internal FIFO write enablesignal (S3). As a result, data 1 as the input data (DIN) are stored inthe internal FIFO circuit 1.

[0070] Time Area C

[0071] The write enable signal (WEp) is asserted, but the internal FIFOread enable signal (S2) is also asserted. Moreover, since the next-stageFIFO status signal (STNF) is at H level, the next-stage FIFO circuit isin a data writable state. In this case, the output data generator 5firstly reads the data 1 stored in the internal FIFO circuit 1 (S4), andtransmits the data 1 as output data (DOUT) to the next-stage FIFOcircuit. Data 2 as input data (DIN) are stored in the internal FIFOcircuit 1. Further, the write counter of the internal FIFO circuit 1counts the data 1 received in the time area B with being delayed by oneclock so as to indicate 1. The internal FIFO status signal (SI),therefore, becomes 1.

[0072] Time Area D

[0073] The internal FIFO read enable signal (S2) is asserted. Moreover,since the next-stage FIFO status signal (STNF) is at H level, the outputdata generator 5 reads the data 2 stored in the internal FIFO circuit 1(S4) and transmits the data 2 as the output data (DOUT) to thenext-stage FIFO circuit. Further, the write counter of the internal FIFOcircuit 1 counts the data 2 received in the time area C with beingdelayed by one clock so as to indicate 2. Further, the read counter ofthe internal FIFO circuit 1 counts the data 1 read in the time area Cwith being delayed by one clock so as to indicate 1. The internal FIFOstatus signal (Si), therefore, becomes 1.

[0074] Time Area E

[0075] The write enable signal (WEp) is asserted, but since thenext-stage FIFO status signal (STNF) is at L level, the internal FIFOwrite enable generator 3 asserts the internal FIFO write enable signal(S3). As a result, the data 3 as the input data (DIN) are stored in theinternal FIFO circuit 1. Moreover, the read counter of the internal FIFOcircuit 1 counts the data 2 read in the time area D with being delayedby one clock so as to indicate 2. The internal FIFO status signal (Si),therefore, becomes 0.

[0076] Time Area F

[0077] Since data 3 are stored in the internal FIFO circuit 1 and thenext-stage FIFO status signal (STNF) is at H level, the internal FIFOread enable generator 4 asserts the internal FIFO read enable signal(S2). As a result, the output data generator 5 reads the data 3 storedin the internal FIFO circuit 1 (S4), and transmits the data 3 as theoutput data (DOUT) to the next-stage FIFO circuit. Moreover, the readcounter of the internal FIFO circuit 1 has already counted the data 3read in the time area E with being delayed by one clock so as toindicate 3. The internal FIFO status signal (Si) is, therefore, 1.

[0078] Time Area G

[0079] The write enable signal (WEp) is asserted, but since thenext-stage FIFO status signal (STNF) is at L level, the internal FIFOwrite enable generator 3 asserts the internal FIFO write enable signal(S3). As a result, data 4 as the input data (DIN) are stored in theinternal FIFO circuit 1. Moreover, the read counter of the internal FIFOcircuit 1 has counted the data 3 read in the time area F with beingdelayed by one clock so as to indicate 3. The internal FIFO statussignal (Si) is, therefore, 0.

[0080] Time Area H

[0081] Since the data 4 are stored in the internal FIFO circuit 1 andthe next-stage FIFO status signal (STNF) is at H level, the internalFIFO read enable generator 4 asserts the internal FIFO read enablesignal (S2). As a result, the output data generator 5 reads the data 4stored in the internal FIFO circuit 1 (S4), and transmits the data 4 asthe output data (DOUT) to the next FIFO circuit. Further, the writecounter of the internal FIFO circuit 1 has already counted the data 4read in the time area G with being delayed by one clock so as toindicate 4. Further, the read counter of the internal FIFO circuit 1 hasalready counted the data 3 read in the time area F with being delayed byone clock so as to indicate 4. The internal FIFO status signal (S1) is,therefore, 0.

[0082] The above-mentioned operation of the concrete example 1 iscompiled so as to be summarized in the following logic.

[0083] (1) When the next-stage FIFO circuit is in a writable state,namely, when the next-stage FIFO circuit is empty, the Extending circuitfor memory transmits input data directly to the next-stage FIFO circuit.The time area A in FIG. 3 corresponds to this case.

[0084] (2) When the next-stage FIFO circuit is in an unwritable state,namely, the next-stage FIFO circuit is full (not empty), the Extendingcircuit for memory stores the input data into the internal FIFO circuit1. The time areas B and E in FIG. 3 correspond to this case.

[0085] (3) When the next-stage FIFO circuit is in a writable state,namely, when the next-stage FIFO circuit is empty and data are stored inthe internal FIFO circuit, the Extending circuit for memory transmitsthe data stored in the internal FIFO circuit to the next-stage FIFOcircuit. The time areas F and H in FIG. 3 correspond to this case.

[0086] (4) When the next-stage FIFO circuit is in a writable state,namely, when the next-stage FIFO circuit is empty and data are stored inthe internal FIFO circuit and the input data are received, the Extendingcircuit for memory preferentially transmits the data stored in theinternal FIFO circuit to the next-stage FIFO circuit. The time area C inFIG. 3 corresponds to this case.

[0087] In the above explanation, the Extending circuit for memory isoperated by one clock signal (CLK), but the present invention is notlimited to this example. That is to say, the clock signal of the datainput is not necessarily equal with the clock signal of the data output,and thus clock signals with different timings may be used. Moreover, inthe above explanation, the status signal (ST) represents a quantity ofthe data stored in the internal memory, but the present invention is notlimited to this example. That is to say, any signal may be used as longas it can discriminate whether the internal memory is full or empty.

[0088] Further, the above explanation refers to only the case where oneExtending circuit for memory of the present invention is added beforeand after the existent FIFO circuit, but the present invention is notlimited to this example. Another example is explained with reference tothe drawing.

[0089]FIG. 4 is a connecting diagram of an FIFO module using theExtending circuit for memory.

[0090] As shown in FIG. 4, the Extending circuit for memorys 10-1 to10-n of the present invention are connected with the existent FIFOcircuit 11 in a dependent manner, so that an FIFO module using theExtending circuit for memorys can be constituted.

[0091] As shown in FIG. 4, DIN of the existent FIFO circuit 11 isconnected with DOUT of the Extending circuit for memory 10-1, WE of theexistent FIFO circuit 11 is connected with NWEO of the Extending circuitfor memory 10-1, and ST of the existent FIFO circuit 11 is connectedwith STNF of the Extending circuit for memory 10-1. In the connectionbetween the Extending circuit for memorys, DIN of the next-stageExtending circuit for memory is connected with DOUT of theprevious-stage FIFO circuit, WEp of the next-stage Extending circuit formemory is connected with NWEO of the previous-stage Extending circuitfor memory, and ST of the next-stage Extending circuit for memory isconnected with STNF of the previous-stage Extending circuit for memory.Further, a clock signal is supplied to all the FIFO circuits. In such amanner, the extended FIFO module can be constituted easily.

[0092] As explained above, when the extending circuit for memory isconstituted, as shown in FIG. 4, the extending circuit for memorys areconnected in the dependent manner, so that the extended FIFO module canbe constituted easily. Moreover, an extending circuit for memory10-(n+1) can be easily added to the extended FIFO module. As a result,when the memory capacity of the FIFO circuit is insufficient, the memorycapacity can be increased instantly and easily as the need arises.

[0093] In this case, with respect to the extending circuit for memory10-(n+1), the extending circuit for memory 10-n became the external FIFOcircuit i.e. the next-stage FIFO circuit.

[0094] Moreover, with respect to the previous-stage extending circuit,the next-stage extending circuit for memory is used as the external FIFOcircuit.

CONCRETE EXAMPLE 2

[0095] In this concrete example, the transmitting-receiving device usingextending circuit for memory which is capable of carrying outtransmission and reception using the FIFO circuit with a small memorycapacity is realized. There is a possibility that the memory capacity ofeither the existent transmission FIFO circuit or reception circuit isinsufficient, and the other memory capacity is enough according to achange in the service condition of the communication device. Further,this situation may be abruptly reversed.

[0096] In such a case, the Extending circuit for memorys realized in theconcrete example 1 can be connected with the reception FIFO circuit orthe transmission FIFO circuit in a switching manner. In order to achievethis object, the transmitting-receiving device using extending circuitfor memory in this concrete example is constituted as follows.

[0097]FIG. 5 is a block diagram of the transmitting-receiving deviceusing extending circuit for memory using the Extending circuit formemory.

[0098] With reference to FIG. 5, the transmitting-receiving device usingextending circuit for memory using the Extending circuit for memorycomprises an Extending circuit for memory 10, a transmission FIFOcircuit 21, a reception FIFO circuit 22, a first selector 23, a secondselector 24, a third selector 25 and a fourth selector 26.

[0099] The first selector can connect either a transmission signalsystem 27 or a reception signal system 28 with the Extending circuit formemory 10 in a switching manner.

[0100] The second selector can connect a status signal from either thetransmission FIFO circuit 21 or the reception FIFO circuit 22 with theinternal FIFO write enable generator 3 (FIG. 1), the output dataeffective signal generator 2 (FIG. 1), and the internal FIFO read enablegenerator 4 (FIG. 1) of the Extending circuit for memory 10 in aswitching manner.

[0101] The selector 3 can connect either the output data generator 5(FIG. 1) and the output data effective signal generator 2 (FIG. 1) ofthe Extending circuit for memory 10 or the transmission signal system 27with the transmission FIFO circuit 21 in a switching manner.

[0102] The selector 4 can connect either the output data generator 5(FIG. 1) and the output data effective signal generator 2 (FIG. 1) ofthe Extending circuit for memory 10 or the transmission signal system 28with the transmission FIFO circuit 22 in a switching manner.

[0103] The first selector 23, the second selector 24, the third selector25 and the fourth selector 26 are switched so that the Extending circuitfor memory 10 can be connected with either the transmission FIFO circuit21 or the reception FIFO circuit 22. As a result, in the case where thememory capacity of the transmission FIFO circuit 21 is insufficient andthe memory capacity of the reception FIFO circuit 22 is sufficient, theExtending circuit for memory 10 can be connected with the transmissionFIFO circuit 21. Further, in the case where the memory capacity of thetransmission FIFO circuit 21 is sufficient and the memory capacity ofthe reception FIFO circuit 22 is insufficient, the Extending circuit formemory 10 can be connected with the reception FIFO circuit 22.

[0104] The memory capacity of the transmission FIFO circuit 21 and thememory capacity of the reception FIFO circuit 22 are determined as totheir sufficient/insufficient state based on the respective statussignals. A control unit for automatically switching the first selector23, the second selector 24, the third selector 25, and the fourthselector is further provided, so that the transmitting-receiving deviceusing extending circuit for memory, which is capable of switching moreaccurately at higher speed, can be obtained.

[0105] The above explanation refers to only the switching between thetwo FIFO circuits of the transmission FIFO circuit 21 and the receptionFIFO circuit 22, but the present invention is not limited to thisexample. That is to say, the switching among three or more FIFO circuitscan be realized by the similar technique.

[0106] The constitution of the concrete example 2 explained above isadopted, so that the Extending circuit for memory can be connected witheither the transmission FIFO circuit or the reception FIFO circuit. Forthis reason, in the case where the memory capacity of the transmissionFIFO circuit is insufficient and the memory capacity of the receptionFIFO circuit is sufficient, the Extending circuit for memory can beconnected with the transmission FIFO circuit. Moreover, in the oppositecase, the Extending circuit for memory can be connected with thereception FIFO circuit. As a result, the memory capacity of theExtending circuit for memory can be utilized effectively.

EFFECTS OF THE INVENTION

[0107] The Extending circuit for memory is constituted as explainedabove, so that the following effects can be obtained.

[0108] 1. The Extending circuit for memorys are connected in a dependentmanner so that the extended FIFO module can be constituted easily.

[0109] 2. The Extending circuit for memory can be further added to theextended FIFO module easily.

[0110] 3. As a result, in the case where the memory capacity of the FIFOcircuit is insufficient, the memory capacity can be increased laterinstantly and easily as the need arises.

[0111] 4. Further, the Extending circuit for memory of the presentinvention is used in the transmitting-receiving device using extendingcircuit for memory and connected with the reception FIFO circuit or thetransmission FIFO circuit instantly in a switching manner, so that theExtending circuit for memory can be connected with either thetransmission FIFO circuit or the reception FIFO circuit. For thisreason, in the case where the memory capacity of the transmission FIFOcircuit is insufficient and the memory capacity of the reception FIFOcircuit is sufficient, the Extending circuit for memory can be connectedwith the transmission FIFO circuit. Further, in the opposite situation,the Extending circuit for memory can be connected with the receptionFIFO circuit. As a result, the memory capacity of the Extending circuitfor memory can be utilized effectively.

What is claimed is:
 1. An extending circuit for memory which has aninternal FIFO circuit and is connected with an external FIFO circuit, inorder to extend memory capacity used for writing input data, comprising:an output data effective signal generator which, when, based on a statussignal output from said external FIFO circuit, judged that said externalFIFO circuit can write data, makes said external FIFO circuit performwriting operation, for outputting said input data into said externalFIFO circuit; and an internal FIFO write enable generator which, when,based on said status signal output from said external FIFO circuit,judged that said external FIFO circuit can not write data, makes saidinternal FIFO circuit perform writing operation, for writing said inputdata into said internal FIFO circuit.
 2. The extending circuit formemory according to claim 1, further comprising: an internal FIFO readenable generator which, when, based on said status signal output fromsaid external FIFO circuit and a status signal output from said internalFIFO circuit, judged that said external FIFO circuit can write data andsaid internal FIFO circuit is having memory data, makes said internalFIFO circuit perform reading operation, for read said memory data outfrom said internal FIFO circuit and outputting said memory data to saidexternal FIFO circuit; and an output data generator which, when saidexternal FIFO circuit is judged being able to write data; and saidinternal FIFO circuit is judged having memory data; and said input datais received, outputs, prior to said input data, said memory data readout from said internal FIFO circuit to said external FIFO circuit.
 3. Atransmitting-receiving device using the extending circuit for memoryaccording to claim 2 for extending memory to be connected with either atransmission FIFO circuit or a reception FIFO circuit in a switchingmanner in order to extend a memory capacity, the transmitting-receivingdevice using extending circuit for memory using the Extending circuitfor memory comprising: a first selector for enabling either atransmission signal system or a reception signal system to be connectedwith the Extending circuit for memory in a switching manner; a secondselector for enabling a status signal from either the transmission FIFOcircuit or the reception FIFO circuit to be connected with the internalFIFO write enable generator, the output data effective signal generator,and the internal FIFO read enable generator of the Extending circuit formemory in a switching manner; a third selector for enabling thetransmission FIFO circuit to be connected with either the output datagenerator and the output data effective signal generator of theExtending circuit for memory or the transmission signal system in aswitching manner; and a fourth selector for enabling the reception FIFOcircuit to be connected with either the output data generator and theoutput data effective signal generator of the Extending circuit formemory or the reception signal system in a switching manner.
 4. Thetransmitting-receiving device using extending circuit for memory usingthe Extending circuit for memory according to claim 3, furthercomprising: a control section for: receiving status signals from thetransmission FIFO circuit and the reception FIFO circuit, when thetransmission FIFO circuit is in a data writable state and the receptionFIFO circuit is in a data unwritable state, connecting the firstselector with the reception signal system and connecting the second andthe third selectors with the reception selector in a switching manner,and receiving the status signals from the transmission FIFO circuit andthe reception FIFO circuit, when the reception FIFO circuit is in a datawritable state and the transmission FIFO circuit is in a data unwritablestate, connecting the first selector with the transmission signal systemand connecting the second and the third selectors with the transmissionselector in a switching manner.